Changes between Version 30 and Version 31 of SIMD


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Timestamp:
Nov 16, 2011 4:55:21 PM (4 years ago)
Author:
gmainland
Comment:

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  • SIMD

    v30 v31  
    601601 * [wiki:SimdLlvm SIMD LLVM] A previous (LLVM-specific) iteration of this SIMD proposal.
    602602 * [wiki:VectorComputing VectorComputing]  A previous proposal to make use of x86 SSE in GHC.
     603
     604= Current Implementation Status =
     605
     606The prototype implementation of the above specification is vailable as the `simd` branch of GHC.
     607
     608== General plan ==
     609
     610=== Vector types ===
     611
     612Vectors of the following types are implemented: `Int32`, `Int64`, `Float`, and `Double`.
     613
     614=== Fixed and variable sized vectors ===
     615
     616For each type, currently only one vector width is implemented, namely the width that is appropriate for SSE2. This means that vectors are currently all 16 bytes in size.
     617
     618== Code generators ==
     619
     620Only the LLVM code generator is supported.
     621
     622== Cmm layer ==
     623
     624Our `CmmType` representation for vectors differs slightly from the proposal. See [source:/compiler/cmm/CmmType.hs?rev=e42746d07239888c74e937046fadf93655b44b65#L42 cmm/CmmType.hs].
     625
     626See [source:/compiler/cmm/CmmMachOp.hs?rev=e42746d07239888c74e937046fadf93655b44b65#L106 cmm/CmmMachOp.hs] for the new vector MachOps.
     627
     628== Core layer ==
     629
     630The implementation differs from the proposal in its naming scheme. We wanted to avoid overloading the term "vector," so, e.g., a 4-wide SIMD vector of `Float#`s is a `FloatX4#`.
     631
     632See [source:/compiler/prelude/primops.txt.pp?rev=e42746d07239888c74e937046fadf93655b44b65#L1935 compiler/prelude/primops.txt.pp] for the new primops. Not everything in the proposal is implemented, but we do have a useful subset.
     633
     634== Native vector sizes ==
     635
     636This is unimplemented. Instead we define a higher-level `Multi` data family whose instance is platform-dependent. For example, a `Multi Int` is represented using an `Int32X4#` on a 32-bit platform, and by a `Int64X2#` on a 64-bit platform.
     637
     638== ABIs and calling conventions ==
     639
     640Integrating variable-sized vectors with GHC's calling convention is a challenge. How many new registers do we add? Do we add registers for each vector type? The correct approach is unclear, so the current implementation passes all SIMD vectors on the stack.
     641
     642=== Memory alignment for vectors ===
     643
     644The implementation does not attempt to align memory containing SIMD vectors. SIMD vector loads and stores do not assume alignment.