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Apr 16, 2012 12:36:13 PM (
The prototype implementation of the above specification is vailable as the `simd` branch of GHC.
== General plan ==
=== Vector types ===
Vectors of the following types are implemented: `Int32`, `Int64`, `Float`, and `Double`.
=== Fixed and variable sized vectors ===
For each type, currently only one vector width is implemented, namely the width that is appropriate for SSE2. This means that vectors are currently all 16 bytes in size.
== Code generators ==
Only the LLVM code generator is supported.
== Cmm layer ==
Our `CmmType` representation for vectors differs slightly from the proposal. See [source:/compiler/cmm/CmmType.hs?rev=e42746d07239888c74e937046fadf93655b44b65#L42 cmm/CmmType.hs].
See [source:/compiler/cmm/CmmMachOp.hs?rev=e42746d07239888c74e937046fadf93655b44b65#L106 cmm/CmmMachOp.hs] for the new vector MachOps.
== Core layer ==
The implementation differs from the proposal in its naming scheme. We wanted to avoid overloading the term "vector," so, e.g., a 4-wide SIMD vector of `Float#`s is a `FloatX4#`.
See [source:/compiler/prelude/primops.txt.pp?rev=e42746d07239888c74e937046fadf93655b44b65#L1935 compiler/prelude/primops.txt.pp] for the new primops. Not everything in the proposal is implemented, but we do have a useful subset.
== Native vector sizes ==
This is unimplemented. Instead we define a higher-level `Multi` data family whose instance is platform-dependent. For example, a `Multi Int` is represented using an `Int32X4#` on a 32-bit platform, and by a `Int64X2#` on a 64-bit platform.
== ABIs and calling conventions ==
Integrating variable-sized vectors with GHC's calling convention is a challenge. How many new registers do we add? Do we add registers for each vector type? The correct approach is unclear, so the current implementation passes all SIMD vectors on the stack.
=== Memory alignment for vectors ===
The implementation does not attempt to align memory containing SIMD vectors. SIMD vector loads and stores do not assume alignment.