Changes between Version 25 and Version 26 of Commentary/Compiler/Backends/NCG/RegisterAllocator


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Timestamp:
Sep 19, 2007 4:03:57 PM (7 years ago)
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guest
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  • Commentary/Compiler/Backends/NCG/RegisterAllocator

    v25 v26  
    120120   For the architectures currently supported, x86, x86_64 and ppc, the native code generator currently emits code using only two register classes {{{RcInteger}}} and {{{RcDouble}}}. As these classes are disjoint (ie, none of the regs from one class alias with with regs from another), checking whether a node of a certain class is trivially colorable reduces to counting up the number of neighbours of that class. 
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    122   If the NCG starts to use aliasing register classes eg: both 32bit {{{RcFloat}}}s and 64bit {{{RcDouble}}}s on sparc; combinations of 8, 16, and 32 bit integers on x86 / x86_x6 or usage of sse / altivec regs in different modes, then this can be supported via the method described in [Smith et al]. The allocator was designed with this in mind - ie, by passing a function to test if a node is trivially colorable as a parameter to the coloring function - and there is already a description of the register set for X86 in [[GhcFile(compiler/nativeGen/RegArchX86.hs)]], but the native code generator doesn't currently emit code to test it against. 
     122  If the NCG starts to use aliasing register classes eg: both 32bit {{{RcFloat}}}s and 64bit {{{RcDouble}}}s on sparc; combinations of 8, 16, and 32 bit integers on x86 / x86_x6 or usage of sse / altivec regs in different modes, then this can be supported via the method described in [Smith et al]. The allocator was designed with this in mind - ie, by passing a function to test if a node is trivially colorable as a parameter to the coloring function - and there is already a description of the register set for x86 in [[GhcFile(compiler/nativeGen/RegArchX86.hs)]], but the native code generator doesn't currently emit code to test it against. 
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