Building/ARMLinuxGnuEABI: llvm-2011-07-12.patch

File llvm-2011-07-12.patch, 4.9 KB (added by chak, 4 years ago)

Patch against LLVM 2011-07-12

  • lib/Target/ARM/ARMBaseRegisterInfo.cpp

    diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    index f231089..01b60be 100644
    a b ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 
    6565 
    6666const unsigned* 
    6767ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 
     68  bool ghcCall = false; 
     69 
     70  if (MF) { 
     71    const Function *F = MF->getFunction(); 
     72    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 
     73  } 
     74 
    6875  static const unsigned CalleeSavedRegs[] = { 
    6976    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 
    7077    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4, 
    ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 
    8491    ARM::D11, ARM::D10, ARM::D9,  ARM::D8, 
    8592    0 
    8693  }; 
    87   return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 
     94 
     95  static const unsigned GhcCalleeSavedRegs[] = { 
     96    0 
     97  }; 
     98 
     99  return ghcCall ? GhcCalleeSavedRegs : 
     100         STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 
    88101} 
    89102 
    90103BitVector ARMBaseRegisterInfo:: 
  • lib/Target/ARM/ARMCallingConv.td

    diff --git a/lib/Target/ARM/ARMCallingConv.td b/lib/Target/ARM/ARMCallingConv.td
    index d2981c0..47b2e98 100644
    a b def RetFastCC_ARM_APCS : CallingConv<[ 
    8282  CCDelegateTo<RetCC_ARM_APCS> 
    8383]>; 
    8484 
     85//===----------------------------------------------------------------------===// 
     86// ARM APCS Calling Convention for GHC 
     87//===----------------------------------------------------------------------===// 
     88 
     89def CC_ARM_APCS_GHC : CallingConv<[ 
     90  // Handle all vector types as either f64 or v2f64. 
     91  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 
     92  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 
     93 
     94  CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 
     95  CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, 
     96  CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, 
     97 
     98  // Promote i8/i16 arguments to i32. 
     99  CCIfType<[i8, i16], CCPromoteToType<i32>>, 
     100 
     101  // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim 
     102  CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>> 
     103]>; 
    85104 
    86105//===----------------------------------------------------------------------===// 
    87106// ARM AAPCS (EABI) Calling Convention, common parts 
  • lib/Target/ARM/ARMFastISel.cpp

    diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
    index f469d7e..95874c5 100644
    a b CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) { 
    15311531    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 
    15321532  case CallingConv::ARM_APCS: 
    15331533    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 
     1534  case CallingConv::GHC: 
     1535    if (Return) 
     1536      llvm_unreachable("Can't return in GHC call convention"); 
     1537    else 
     1538      return CC_ARM_APCS_GHC; 
    15341539  } 
    15351540} 
    15361541 
  • lib/Target/ARM/ARMFrameLowering.cpp

    diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp
    index 4ef2666..9440a85 100644
    a b  
    1616#include "ARMBaseInstrInfo.h" 
    1717#include "ARMBaseRegisterInfo.h" 
    1818#include "ARMMachineFunctionInfo.h" 
     19#include "llvm/CallingConv.h" 
     20#include "llvm/Function.h" 
    1921#include "llvm/CodeGen/MachineFrameInfo.h" 
    2022#include "llvm/CodeGen/MachineFunction.h" 
    2123#include "llvm/CodeGen/MachineInstrBuilder.h" 
    void ARMFrameLowering::emitPrologue(MachineFunction &MF) const { 
    138140  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 
    139141  int FramePtrSpillFI = 0; 
    140142 
     143  // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue. 
     144  if (MF.getFunction()->getCallingConv() == CallingConv::GHC) 
     145    return; 
     146 
    141147  // Allocate the vararg register save area. This is not counted in NumBytes. 
    142148  if (VARegSaveSize) 
    143149    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize, 
    void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 
    325331  int NumBytes = (int)MFI->getStackSize(); 
    326332  unsigned FramePtr = RegInfo->getFrameRegister(MF); 
    327333 
     334  // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue. 
     335  if (MF.getFunction()->getCallingConv() == CallingConv::GHC) 
     336    return; 
     337 
    328338  if (!AFI->hasStackFrame()) { 
    329339    if (NumBytes != 0) 
    330340      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 
  • lib/Target/ARM/ARMISelLowering.cpp

    diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
    index b0425f1..4598d98 100644
    a b CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 
    10751075    return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 
    10761076  case CallingConv::ARM_APCS: 
    10771077    return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 
     1078  case CallingConv::GHC: 
     1079    return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC); 
    10781080  } 
    10791081} 
    10801082